bi-cmos 12-bit serial-input latched driver m 549 77 p mitsubishi 20 17 18 19 1 4 3 2 16 5 15 6 14 7 13 8 12 9 11 10 des cri pt i o n the M54977p i s a semiconductor integrated circuit fabricated using bi-cmos technology. i t contains a serial input t o serial/parallel output 12-bit cmos shift register and cmos latch as well as bipolar 12-bit parallel-output driver. f e at ures l serial input to serial/parallel output l cascade connections possible through serial output l latch circuit included for each stage l enable input for output control l low supply current .................................. i cc 3 10 m a at standby l serial input/output level is compatible with standard cmos l driver : withstand voltage ...................................... bv ceo 3 30v large drive current ................................ (i o(max) =200ma) l wide operating temperature range ..................... t a =-20 ? +75 c app l i cat i o n thermal printer head dot driver, serial-to parallel conversion, relay, solenoid driver f unct i o n the M54977p consists of an 12-bit d-type flip-flop, the output o f which is connected to 12 latches. when data is applied to the serial data input (s-in) and a clock pulse is applied to clock input (t), an ?? to ?? change of the clock will cause the data input signals to enter the internal shift registers and the data in the shift registers will be shifted in order. using a number o f M54977p units for bit expansion i n series will entail connecting serial output (s-out) to s-in of the next-stage M54977p. in parallel output, when the latch input is set to ?? and the output- control input (enable input en) is ?? a clock pulse changing from ?? to ?? will cause the serial data input signal to appear at output o1, and the data will be shifted in order at outputs o2 ? o12. the parallel output will yield a signal that is inverted with respect to the serial data input. b l oc k d ia gr a m pi n c o n f i g urat i o n ( to p v i e w ) ? ? ? ? ? ? ? ? ? ? ? ? ? t s-in l-gnd v cc s-out latch en p-gnd o1 o2 o3 o4 o5 o6 o7 o8 clock serial input logic gnd serial output latch input enable input driver gnd parallel outputs outline 20p4 m5 4977p ? ? o9 o10 ? o12 ? o11 parallel outputs q l d o1 clock t q t d q l d o2 q t d q l d o3 q t d q l d o4 q t d q l d o5 q t d q l d o6 q t d q l d o7 q t d q l d o8 q t d q l d o9 q t d q l d o10 q t d q l d o11 q t d q l d o12 q t d en s-out serial output p -gnd driver gnd parallel outputs power supply v cc latch input latch serial input s-in enable input 3 1 2 6 4 7 10 5 20 19 18 17 16 15 14 13 12 11 9 8 l-gnd
bi-cmos 12-bit serial-input latched driver m 549 77 p mitsubishi setting the latch input to ?? will prevent data from entering t h e latch. when the en input is set to ?? all outputs (o1 ? o12) will be set to off. since the internal logic state of the ic is uncertain a t power-on time, set the en input to ?? (and outputs o1 ? o12 will set t o off) until the input data i s set and the internal logic state has been determined. l-gnd is the ground of the cmos logic circuit section and p-gnd is the ground for the output driver section (o1 ? o12), which i s made up of bipolar transistors that are capable of driving large currents. t i m i ng chart *the state of the shaded part is unstable. s-in serial input t clock latch latch input en enable input s-out serial output o1 o2 o3 o4 o5 o6 o7 o8 parallel outputs o9 o10 o11 o12
bi-cmos 12-bit serial-input latched driver m 549 77 p mitsubishi i nput / o ut p ut ci rc ui t di ag ram 1 2 3 4 inputs with pullup resistor (en, latch) inputs with pulldown resistor (t, s-in) parallel output (o1 ? o12) serial output (s-out) r in v cc l-gnd v cc l-gnd r in v cc l-gnd l-gnd p -gnd 1.5k w
bi-cmos 12-bit serial-input latched driver m 549 77 p mitsubishi o1 ? o12 : off symbol ratings unit parameter conditions abs o l ut e m axi m um rat i ng s (t a =-20 to 75 c, unless otherwise noted) v cc v i v o i o p d t opr t stg supply voltage input voltage output voltage output current power dissipation operating temperature storage temperature s-out t a =25 c 0 ? 7 0 v cc 0 v cc 0 3 0 25 0 1.25 -55 ? 125 v v v ma w c limits min. typ. max. symbol conditions unit parameter rec o m m e nde d o perat i n g c o ndi t i o n (t a =-20 to 75 c, unless otherwise noted) v cc v o i o supply voltage applied o utput voltage output current (per circuit) o1 ? o12 : off all outputs go in the on state simultaneously. duty cycle < 20% 45 6 30 200 v v ma limits min. typ. max. symbol test conditions unit parameter el ect r i cal charact eri s t i cs (t a =25 c, v cc =5v, unless otherwise noted) v ih v il v oh v ol i oh i ol v ol1 i olk i cc 1 i cc 2 high-level input voltage low-level input voltage input resistance high-level output voltage low-level output voltage high-level output current low-level output current supply current output leak current t a =-20 ?75 c, v cc =4 ? 6v v oh =4.5v i ol =100ma i ol =200ma input: open, all driver outputs: off 0.7v cc 0 50 4.9 -100 400 v cc 0.3v cc 0.1 1.2 1.4 v v k w v v m a m a v -20 ? 75 r in v ol2 low-level output voltage |i o | 1 m a v o =30v v ol =0.4v one driver output is on. 50 10 1.25 v m a m a ma c s-out s-out s-out s-out o1 o12 o1 o12
bi-cmos 12-bit serial-input latched driver m 549 77 p mitsubishi t f (t) clock pulse fall time limits min. typ. max. symbol test conditions unit parameter sw i t chi ng chara ct e r i s t i cs (t a =25 c, v cc =5v, unless otherwise noted) t plh t phl t plh t phl t plh t phl low-to-high-level output propagation time, from input t to output s-out (0.15) 0.3 m s t i m i ng chart limits min. typ. max. symbol test conditions unit parameter t i m i ng req u i r e m e n t s (t a =-20 to 75 c, unless otherwise noted) f (t) t w(t) t w(l) t su t h t d(t-l) t r(t) clock frequency clock pulse width latch pulse width data setup time data hold time clock-latch time clock pulse rise time input duty cycle: 40 ? 60% 200 200 100 100 400 2 500 500 mhz ns ns ns ns ns ns ns high-to-low-level output propagation time, from input t to output s-out low-to-high-level output propagation time, from input t to output o n high-to-low-level output propagation time, from input t to output o n low-to-high-level output propagation time, from input en to output o n high-to-low-level output propagation time, from input en to output o n v ih =5v v il =0v r l (s-out )= r l (o n )=100 w (n=1?2) c l =15pf (0.15) (2) (0.5) (2) (0.5) 0.3 10 2 10 2 m s m s m s m s m s t i m i ng chart t su 2.5v t h t w(t) t r(t) s-in t latch 2.5v 2.5v 2.5v 90% 10 % t d(t-l) t w(l) 2.5v 2.5v t f(t) 90% 10 % serial input clock latch input 2.5v t plh 2.5v s-out t 2.5v t phl 2.5v 2.5v 2.5v 2.5v 2.5v 2.5v t plh 2.5v t plh t phl en o n t phl serial output clock enable input output
bi-cmos 12-bit serial-input latched driver m 549 77 p mitsubishi t est ci rcui t t ypi cal charact eri s t i cs v cc r l c l input pg 50 w m5 4977p output the in put waveform: t r 20ns, t f 20ns the capacitance c l includes the wiring stray capacitance and probe input capacitance. thermal derating 0 0 0.5 1.0 1.5 25 50 75 100 power dissipation p d (w) ambient temperature t a ( c) 0 100 0 100 150 200 50 output current i o (ma) duty cycle (%) 20 40 60 80 0 100 duty cycle vs. allowable output current duty cycle (%) 20 40 60 80 0 100 150 200 50 t a = 75 c repetitive frequency > 10h z each figure in a circle shows the number of output circuits which operate simultaneously. current value : output current per circuit t a = 25 c repetitive frequency > 10h z each figure in a circle shows the number of output circuits which operate simultaneously. current value : output current per circuit duty cycle vs. allowable output current output current i o (ma) 1 3 4 5 6 7 8 9 10 11 12 1 7 8 9 10 11 12 6
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